\input{common/slides_common}

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\title{Formal Verification}
\author{Martin Schoeberl}
\date{\today}
\institute{Technical University of Denmark\\
Embedded Systems Engineering}

\begin{document}

\begin{frame}
\titlepage
\end{frame}

\begin{frame}[fragile]{TODO}
\begin{itemize}
\item Check for overlap with UART in 09 (remove)
\item Add microprocessor bus figures
\item Some words on AXI
\item Also how to map IO devices into a memory space (maybe this is too early, topic of agile HW design, or HW/SW codesign.)
\item Maybe too much repetition?
\item Get new stuff in
\item Add asserts
\item FPGAs and resource requirements
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Overview}
\begin{itemize}
%\item TODO: more from the mid-term eval, e.g., \emph{Potentially utilizing some more memory (BRAM) or potentially some of the hardware interfaces which the Basys 3 Board provides, such as USB and VGA.} This might be in week 11 with serial port. Or I move more stuff into week 10.
%\item TODO: FIFO as example of the ready valid thing (next week)
%\item TODO: FPGA internals
%\item TODO: A bit more about the physical chip design/architechture. When a chip is shown and referes to, and i have no idea what im looking at, its a bit difficult to follow along.
%\item Repeat FSMD (for the vending machine)
%\begin{itemize}
%\item I have seen some intermix of FSM and datapath
%\item Works only for small designs
%\end{itemize}
\item xxx
\begin{itemize}
\item What is your lab status? Display multiplexing working?
\end{itemize}
\end{itemize}
\end{frame}


\begin{frame}[fragile]{Summary}
\begin{itemize}
\item xxx
\end{itemize}
\end{frame}



\end{document}

%\begin{frame}[fragile]{xxx}
%\begin{itemize}
%\item yyy
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